Memory Systems Glossary: Key Terms and Definitions

The memory systems field encompasses a dense technical vocabulary that spans computer architecture, storage engineering, operating systems design, and semiconductor physics. Professionals navigating procurement, system architecture, or standards compliance rely on precise definitions to distinguish functionally distinct technologies. This glossary covers foundational and advanced terms organized by conceptual scope, drawing on established definitions from IEEE, JEDEC, and NIST standards bodies.

Definition and scope

A memory systems glossary serves as a normative reference for terms that describe how digital systems store, retrieve, and manage data at every level of the memory hierarchy. The scope spans volatile and nonvolatile storage, logical addressing constructs, performance metrics, and fault management terminology.

Key classification boundaries apply:

The IEEE Standard 610.12 glossary of software engineering terminology and JEDEC Publication 21C provide foundational definitional anchors for the hardware-facing terms listed throughout this reference. NIST's Computer Security Resource Center (CSRC) defines memory-related security terms including memory isolation and side-channel vulnerability classifications.

How it works

Memory system terminology is structured around four primary axes: addressing mode, access latency, persistence, and error behavior. Understanding where a given term falls along each axis determines how it maps to system design constraints.

Core terms by axis:

  1. Addressing mode
  2. Byte-addressable: Every individual byte has a unique address. DRAM and persistent memory operate in this mode.
  3. Block-addressable: Data is read and written in fixed-size blocks (e.g., 4 KB pages for NAND flash). Block size directly governs write amplification.

  4. Content-addressable: A cache lookup mechanism where data is retrieved by value rather than address — implemented in hardware as a CAM (Content-Addressable Memory).

  5. Access latency classification

  6. L1/L2/L3 cache: On-chip SRAM caches with latencies measured in single-digit to tens of nanoseconds. Intel and AMD publicly specify cache latencies in processor data sheets.
  7. Main memory (DRAM): Latencies of approximately 60–80 nanoseconds for DDR4 at standard speeds (Micron Technology DRAM data sheets).

  8. NVM (nonvolatile memory): Latencies range from 300 nanoseconds (3D XPoint) to 100+ microseconds (NAND flash).

  9. Persistence classes

  10. Ephemeral: Data lost on power removal.

  11. Persistent: Data survives power cycling. Governed by endurance ratings measured in Program/Erase (P/E) cycles.

  12. Error behavior

  13. Hard error: Permanent physical failure requiring replacement.
  14. Soft error: Transient bit flip caused by radiation or electrical noise, correctable via ECC (Error-Correcting Code). JEDEC JESD89 standard defines the test methodology for soft error rate measurement. Detailed correction mechanisms appear in memory error detection and correction.

Common scenarios

Memory terminology appears in 3 primary professional contexts, each emphasizing distinct vocabulary subsets:

System architecture and procurement: Engineers specifying server configurations reference terms such as memory rank, DIMM (Dual Inline Memory Module), memory channel width, and CAS latency (Column Address Strobe latency). A dual-rank DDR5 DIMM operating at 4800 MT/s delivers a theoretical peak bandwidth of 38.4 GB/s per channel. JEDEC JESD79-5 governs DDR5 electrical specifications.

Operating systems and virtualization: Virtual memory concepts dominate this layer. The virtual memory systems reference covers paging, segmentation, TLB (Translation Lookaside Buffer), and page fault handling. Key terms here include working set (the set of pages actively used by a process within a defined time window) and thrashing (a pathological condition where excessive page faults saturate I/O bandwidth).

Security and compliance: Memory security terminology includes terms such as rowhammer (an exploit targeting DRAM cell charge leakage), memory-safe language (a language enforcing bounds checking by design), and ASLR (Address Space Layout Randomization). NIST SP 800-160 Vol. 1 addresses memory protection within systems security engineering frameworks (NIST SP 800-160).

Decision boundaries

Selecting the correct term — particularly in standards documentation or procurement specifications — requires resolving 3 common definitional ambiguities:

RAM vs. memory: RAM (Random-Access Memory) denotes access mode, not storage permanence. Flash memory is technically random-access but is conventionally excluded from the "RAM" designation because of its block-write constraint and asymmetric read/write latency.

Cache vs. buffer: A cache stores copies of frequently accessed data to reduce latency. A buffer temporarily holds data in transit between two components operating at different speeds. The terms are not interchangeable, though both appear in cache memory systems discussions.

Persistent memory vs. storage: Persistent memory operates on the memory bus and exposes byte-addressable interfaces to the CPU. Storage devices (SSDs, HDDs) connect via I/O buses (PCIe, SATA) and require block-layer software abstractions. The persistent memory systems reference maps this boundary in detail.

The full memory systems glossary is a living reference synchronized with JEDEC, IEEE, and NIST terminology updates. Broader context for all terms covered here is available from the Memory Systems Authority index.

References

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