Memory Systems in Embedded and IoT Devices

Embedded and IoT devices operate under constraints that fundamentally reshape how memory systems are selected, configured, and managed. Unlike server or desktop platforms, these devices face hard limits on power consumption, physical footprint, cost per unit, and thermal envelope — all of which drive specialized memory architectures that differ substantially from mainstream computing. This page covers the classification of memory types used in embedded and IoT contexts, the mechanisms governing their operation, the scenarios that determine selection, and the engineering boundaries that define tradeoffs between competing options.

Definition and scope

Memory systems in embedded and IoT devices encompass all storage and working-memory components integrated into microcontroller units (MCUs), microprocessor-based single-board computers, sensor nodes, and connected edge devices. The scope ranges from kilobytes of on-chip SRAM in an 8-bit MCU to gigabytes of LPDDR4 in an industrial gateway running a real-time operating system.

The JEDEC Solid State Technology Association — the primary standards body governing semiconductor memory specifications — publishes the standards that define electrical and timing characteristics for most memory types found in embedded contexts, including the LPDDR family (JESD209 series) and NOR/NAND flash interfaces. The IETF and IEEE jointly address communication-adjacent memory considerations in constrained device standards such as RFC 7228, which classifies constrained nodes by code size, RAM size, and energy availability.

Embedded memory systems divide into two primary categories:

  1. Volatile memory — retains data only while power is applied. SRAM (Static RAM) dominates on-chip volatile storage in MCUs because it requires no refresh cycles and delivers single-cycle access at frequencies up to 200 MHz or higher on modern ARM Cortex-M cores. DRAM variants, specifically LPDDR4 and LPDDR5, serve higher-end embedded processors where larger working memory is required. The LPDDR mobile memory standards page covers these specifications in detail.

  2. Non-volatile memory — retains data without power. NOR flash, NAND flash, and EEPROM are the dominant types. NOR flash supports execute-in-place (XIP), allowing firmware to run directly from the memory array without shadowing into RAM first — a critical capability for cost-constrained MCUs with limited SRAM. NAND flash offers higher density at lower cost per bit but does not support XIP and requires a flash translation layer (FTL) to manage wear leveling.

The volatile-vs-nonvolatile memory classification framework provides the foundational taxonomy that underlies all embedded memory selection decisions.

How it works

Memory access in embedded systems is mediated by the MCU's memory-mapped I/O model. Every memory region — flash, SRAM, peripheral registers, and external memory — occupies a defined address range within a 32-bit or 64-bit address space. The ARM Cortex-M architecture, documented in the ARM Architecture Reference Manual, partitions this space into fixed regions: code (starting at 0x00000000), SRAM (0x20000000), peripherals (0x40000000), and external RAM and device areas above that.

The memory hierarchy in computing model applies in a compressed form in embedded contexts. On-chip SRAM serves as the working memory layer, typically ranging from 2 KB in the smallest MCUs to 1 MB or more in application processors. Below that sits flash storage — either on-chip NOR flash (common in the 64 KB to 2 MB range) or external NAND/NOR flash connected via SPI or QSPI interfaces.

Wear leveling is a governing constraint for any embedded system using NAND flash or EEPROM. NAND flash cells tolerate between 1,000 and 100,000 program/erase cycles depending on cell type — Single-Level Cell (SLC) at the high end, Triple-Level Cell (TLC) at the low end (JEDEC JESD79F). An FTL distributes writes across the array to prevent premature cell exhaustion, which is especially critical in IoT devices logging sensor data at high frequency.

Power state management ties directly to memory architecture. Many MCUs implement multiple sleep modes in which SRAM contents are preserved (data retention mode) while the CPU and peripherals are powered down, drawing as little as 1–2 µA. The ability to retain SRAM state without re-initializing from flash is a primary driver of SRAM sizing decisions in battery-operated IoT nodes.

Common scenarios

Firmware storage in constrained sensor nodes: A Bluetooth Low Energy sensor node with 256 KB of NOR flash stores its firmware image in flash and executes it in-place. The 32 KB of on-chip SRAM holds the call stack, heap, and live sensor buffers. This configuration requires no external memory components, minimizes board area, and enables sub-2 µA sleep current.

Industrial edge gateways: A Modbus-to-MQTT gateway running Linux on a Cortex-A processor typically pairs 512 MB of LPDDR4 with 4–8 GB of eMMC (embedded NAND flash with an integrated FTL controller). The eMMC interface, standardized under JEDEC JESD84, simplifies flash management relative to raw NAND by embedding the FTL in the component itself.

Over-the-air (OTA) firmware update: Dual-bank NOR flash partitioning — splitting the flash array into two equally sized regions, one active and one holding the incoming firmware image — is the dominant OTA pattern for MCU-based devices. The IETF SUIT (Software Updates for Internet of Things) working group has standardized manifest formats and update procedures for constrained devices through RFC 9124 and related documents.

Data logging at the edge: IoT devices collecting environmental or industrial telemetry write records to NAND flash or SD card storage, using circular buffers and wear-leveling algorithms to distribute writes. Error correction is mandatory — raw NAND requires BCH or LDPC error correction codes to achieve acceptable bit error rates across the flash lifetime.

The flash memory technology reference covers the cell-level physics and error correction requirements in detail.

Decision boundaries

Selecting memory architecture for an embedded or IoT device involves discrete tradeoffs across five dimensions:

  1. Volatility vs. persistence: If the application requires data retention through power cycles, non-volatile memory is mandatory. If only working state is needed during active operation, SRAM alone may suffice.

  2. Execute-in-place vs. load-and-run: NOR flash supports XIP; NAND flash does not. MCUs with less than 64 KB of SRAM typically cannot shadow a full firmware image into RAM, making NOR flash or on-chip flash the only viable code storage option.

  3. Density vs. endurance: NAND flash offers 4–10× the storage density of equivalent NOR flash at lower cost per gigabyte but at 10–100× lower endurance per cell. SLC NAND (100,000 P/E cycles) is appropriate for write-intensive industrial logging; TLC NAND (1,000–3,000 P/E cycles) suits consumer IoT devices with infrequent writes.

  4. Power envelope: LPDDR4 provides high bandwidth but consumes substantially more power than SRAM during active operation. SRAM is the appropriate choice for devices spending more than 90% of their time in sleep states. The LPDDR mobile memory standards page details the power state specifications for LPDDR4 and LPDDR5.

  5. Security requirements: Memory security in embedded devices encompasses secure boot (verifying firmware signatures before execution), memory protection units (MPUs) that enforce access boundaries between RTOS tasks, and encrypted flash storage. NIST SP 800-193 (Platform Firmware Resiliency Guidelines) establishes the federal baseline for firmware protection applicable to IoT devices used in government and critical infrastructure contexts. The memory security and vulnerabilities reference covers attack surfaces including rowhammer, cold-boot attacks, and fault injection.

For professionals navigating the broader landscape of memory technology across embedded, server, and cloud contexts, the Memory Systems Authority index provides a structured entry point to the full reference taxonomy. Comparative analysis of volatile and non-volatile options across all computing contexts is available through the volatile vs. nonvolatile memory reference, and the governing standards and industry bodies that define interface specifications are documented at memory standards and industry bodies.

References

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